The IP Cores which are already developed by XESP:

• Reconfigurable Radio processor for radio communication.
• RNS based faster system application.
• The built-in-test processor architecture.
• Reconfigurable Transform Processor.
• IP-Cores for MCUs.

1. Reconfigurable Parallel DSP Processor Design

Motivation :

High performance, flexibility and low power consumptions are the major issues in developing DSP architectures i.e. achieving highest performance at the lowest possible silicon cost. While the ASIC chips provide better performance over other technologies for a specific application, they suffer from inflexibility. On the other hand, FPGAs are flexible but are unable to meet the speed requirement of high speed, advanced signal/image processing applications. However, FPGA does not provide “Highest Performance at Lowest Silicon Cost” for a given signal processing application since they are not optimized for any particular application.
So, there is a need to eliminate the drawback of FPGAs & ASICs by offering an innovative “Reconfigurable DSP Processor” for high end DSP applications providing a balance between flexibility, reconfiguration latency & performance.
ESP microDesign, Inc. a start up U.S. corporation aims "fabless" microelectronics venture by leveraging innovative digital signal processor technology conceived by Dr. Amitabha Sinha This technology will fulfill the unsatisfied desires of embedded application development customers for a very high-performance cost - effect programmable DSP application platform.
XESP has extended its hands in a collaborative effort with ESP microDesign for successful implementation of this Processor along with a design automation tool “ Integrated development Environment(IDE) including Parallel ‘c’ Compiler( an extension to ‘c’)” to facilitate the user for ease in product development.

• Applications Requiring Such High Performance DSP Processors:
• Software defined radios
• Broadband modems
• Image recognition/target detection
• 3G wireless
• Gigabit packet routing
• HDTV
• 3D medical imaging

2. Reconfigurable Radio Processor:

Motivation:

Performance required by “Software Defined Radio (SDR) “poses many challenges in real-time applications because of their high computational complexity and therefore, designing a high performance SDR with high degree of flexibility becomes a major issue. While the fastest programmable DSP processors are unable to meet the speed requirements for SDR, System on chips ( SOCs) are also not suitable because of their limited flexibility.
Recently, FPGAs have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions . Since , the major building blocks for SDR are the signal processing functions , FPGAs are becoming possible hardware platform for SDR . However, FPGAs are not optimized for radio applications and because of their LUT based approach, they can not offer the highest possible performance at the lowest silicon cost for a given signal processing function. XESP addresses these issues by taking up a challenging job design, develop and implement a special purpose Programmable “VLSI radio Processor” for implementing various radio schemes.